Increasing thermal conductivity of thermal interface using carbon nanotubes and CVD

ABSTRACT

The invention relates to a structure of and a process of forming an integrated circuit package that utilizes a thermal interface material layer having an aligned array of carbon nanotubes affixed to a surface of the layer. The thermal interface material is diamond deposited by chemical vapor deposition. The carbon nanotubes are formed by a plasma discharge process on the surface of the CVDD and also may be formed on the surface of the die.

[0001] This application is a continuation of U.S. patent applicationSer. No. 10/170,313, filed Jun. 12, 2002, which is incorporated hereinby reference.

[0002] An integrated circuit package provides increased thermalconductivity to a thermal interface between a circuit die and a thermalmanagement solution such as a heat spreader or a heat sink by forming achemical vapor deposited diamond surface on the thermal managementsolution and growing an array of carbon nanotubes on the surface of theCVDD layer or the circuit die.

BRIEF DESCRIPTION OF THE DRAWINGS

[0003] In order that the manner in which the embodiments of theinvention are obtained, a more particular description of the inventionbriefly described above will be rendered by reference to specificembodiments thereof which are illustrated in the appended drawings.Understanding that these drawings depict only typical embodiments of theinvention that are not necessarily drawn to scale and are not thereforeto be considered to be limiting of its scope, the invention will bedescribed and explained with additional specificity and detail throughthe use of the accompanying drawings in which:

[0004]FIG. 1 is an elevational cross-section of a prior art stack-upschematic of a cooling arrangement for an integrated circuit package;

[0005]FIG. 2 is an elevational cross-section of a CVDD enhanced priorart stack-up;

[0006]FIG. 3 is a detail of the elevational cross-section of a CVDDenhanced prior art stack-up depicted in FIG. 2 showing thermal interfacematerial positioned between the CVDD layer and the die;

[0007]FIG. 4 is a detail of an elevational cross-section of anembodiment of the invention wherein a CVDD enhanced stack-up utilizesnanotubes grown on the die surface;

[0008]FIG. 5 is a detail of an elevational cross-section of a CVDDenhanced stack-up which shows nanotubes grown on the die surface and theCVDD layer;

[0009]FIG. 6 is a detail of an elevational cross section of a CVDDenhanced stack-up which shows nanotubes grown on the CVDD layer of theintegrated heat spreader;

[0010]FIG. 7 is a process flow diagram of a process for coupling acircuit die to a thermal management aid; and

[0011]FIG. 8 is a process flow diagram of another process for coupling acircuit die to a thermal management aid.

DETAILED DESCRIPTION OF THE INVENTION

[0012] The present invention relates to a structure and a process offorming an integrated circuit package that utilizes a thermal interfacematerial layer having an aligned array of carbon nanotubes projectingfrom a surface thereof.

[0013] In order to cool electronic packages such as electronic dies, abare silicon die is covered with an integrated heat spreader which isformed from a thermally conductive material such as copper and serves tolaterally distribute the thermal load provided by hot spots on the diecorresponding, for example, to the areas of highest transistor activity.

[0014] In FIG. 1, there is shown an integrated circuit package 10 whichhas an interposer or substrate 12 on which a die 14 is located adjacentthe substrate 12 and thermally coupled thereto through solder balls 16which are bonded to a surface of die 14 which adjacent to substrate 12.The space between adjacent solder balls 16 and between the surface ofdie 14 and substrate 12 is generally filled with a thermally conductivegel 18. The combination of the thermal conductivity of solder balls 16and thermally conductive gel 18 provides a cooling path for a portion ofthe heat generated by die 14.

[0015] As shown in FIGS. 1 and 2, a copper integrated heat spreader 20is positioned adjacent to a further surface of die 14 which is oppositeto the surface of die 14 which is adjacent to substrate 12. An innersurface 22 of heat spreader 20 is, in prior art packages such as the oneshown in FIGS. 1 and 2, coupled to the surface of die 14 by a firstthermal interface material layer 24 which is a thermally conductivematerial such as thermal grease or some similar material. Finally, theheat spreader 20 is in thermal contact with a copper heat sink 26through a second thermal interface 28. Ambient air 30 flows across heatsink 26 to cool it.

[0016] In the prior art it has also been known to provide a chemicalvapor deposited diamond (CVDD) layer 32 between the die and theintegrated spreader 20 to improve the lateral thermal conductivity ofeither the spreader 20 or the silicon die 14. CVDD layer 32 isillustrated in FIGS. 2 and 3 applied to the inner surface 22 ofintegrated heat spreader 20.

[0017] The thermal conductivity of the copper of the integrated heatspreader is about 395 W/mK while that of the silicon die is about 100W/mK. The thermal conductivity of a CVDD layer is expected to exceed1000 W/mK. It has been found through simulations that CVDD layers havinga thickness of about 450 microns can provide thermal benefits, measuredas a decrease in the total junction-to-ambient thermal resistance, areapproximately 10% of total for CVDD layers applied to the integratedheat spreader, 20% for the CVDD layer applied to the die andapproximately 30% for combined CVDD layers on both the die and theintegrated heat spreader.

[0018] One of the difficulties present with the use of CVDD layersapplied to the die and the heat spreader are the roughness that isinherent with the unpolished deposited diamond surface 34 which ischaracterized by asperities 36 or projections that have sizes measuredin microns. Although it may be possible to reduce the roughness somewhatby performing a polishing operation after the CVD process, such apolishing operation is expected to be a major contributor to the cost ofmanufacture of the product, particularly as the cost of the CVDD processitself decreases. Unfortunately, it also appears to be true that theroughness of the CVDD layer increases with increasing thickness of theCVDD layer despite the fact that increasing the thickness of the CVDDlayer increases the thermal effectiveness of the layers. In the priorart, accommodation of the uneven surface of the die 14 or the innersurface 22 of the integrated heat spreader 20 as well as the lack ofsmoothness of the CVDD layer, whether it is applied to the die or to theintegral heat spreader; a void filling thermal interface material 38 isinserted between the two.

[0019] Addition of aligned nanotubes to the thermal interface, whetherthe nanotubes are single wall or double wall, increases the thermalconductivity between the die and integral heat spreader while allowingthe elimination of the polishing step from the CVDD process. Describedbelow are embodiments of thermal solutions based upon the addition ofnanotubes to the thermal interface between the die and the integratedheat spreader.

[0020]FIG. 4 shows an embodiment of the invention where the single ordouble wall carbon nanotubes 40 are grown on die 14 by a plasmadischarge deposition process available in the art. Once the nanotubes 40are grown on the surface of die 14, one end of nanotubes in the array isfirmly affixed to the die 14. In this embodiment, the thermalconductivity of the nanotubes 40 is in a range of about 1000 to 6000W/m-K as compared to the conductivity of the typical thermal greasethermal interface material of about 1-7 W/m-K. In the embodiment shown,the length of the nanotubes would typically be about 100 microns or lessso that the thermal resistance of the layer would be negligible. Thegrowing of the nanotubes 40 on the surface of die 14 fills the surfaceroughness valleys to provide a nearly uniform layer for the interface. Alimited crush of the nanotubes 40 allows for an excellent thermalconnection between the surface of die 14 and the CVDD coating 32 oninner surface 22 of heat spreader 20. In one embodiment a thermal greasemay be applied to the array of nanotubes 40. In another embodiment,thermal grease is not used. In another embodiment, CVDD coating 32 maybe formed on the surface of a heat sink 26 instead of a spreader 20.

[0021]FIG. 5 illustrates a further embodiment of the invention in whicha structure has nanotubes 40 which are grown from both the CVDD surfaceof heat spreader 20 and the surface of die 14 using a plasma dischargemethod. In this embodiment the nanotubes 40 grown from and affixed tothe opposed surfaces intermesh as the surfaces are mated to provide agood thermal interface, even without the use of thermal grease 38. In afurther embodiment thermal grease 38 can be used in combination with thecarbon nanotubes 40.

[0022]FIG. 6 shows an embodiment of the invention where single or doublewall carbon nanotubes 40 are grown on and affixed to the CVDD layer 32of the integrated heat spreader 20 using a plasma discharge process.Again, the grown nanotubes 40 fill in the surface roughness valleys andasperities 36 and compensate for them. The projecting nanotubes 40 aresubject to limited crushing of the nanotubes 40 into the peak roughnessfeatures 42 of the die 14. Again, in one embodiment, no grease 38 isnecessary to form the thermal interface. In a further embodiment,thermal grease 38 is provided in combination with the nanotubes 40.

[0023]FIG. 7 is a flow chart of an embodiment of the inventive processfor enhancing heat flow from a circuit die to a thermal management aidsuch as a heat spreader or a heat sink. The first stage 72 of theprocess is forming a CVDD layer on a surface of thermal management aid.After the CVDD layer is formed, a further stage 74 an array ofsubstantially aligned nanotubes is grown on one surface of the circuitdie or on the CVDD layer on the thermal management aid. In stage 76 thethermal management aid is mounted to the die with the layer of nanotubesthermally coupling the surface of the circuit die to the CVDD layer ofthe thermal management aid.

[0024]FIG. 8 is a flow diagram of another embodiment of the inventiveprocess for thermally coupling a circuit die to a thermal management aidsuch as a heat spreader or a heat sink. In an initial stage 82 a CVDDlayer is formed on the thermal management aid. In stage 84 a layer ofnanotubes is grown on the CVDD layer. In stage 86 the thermal managementaid is mounted to the die with the layer of nanotubes thermally couplingthe surface of the die to the CVDD layer of the thermal management aid.

[0025] It will be readily understood to those skilled in the art thatvarious changes in the details, material, and arrangements of the partsand method stages which have been described and illustrated in order toexplain the nature of this invention may be made without departing fromthe principles and scope of the invention as expressed in the subjoinedclaims.

What is claimed is:
 1. Apparatus for cooling a circuit die, comprising:a thermal management aid having a CVDD surface; and an array ofsubstantially aligned carbon nanotubes coupling a surface of the circuitdie to the CVDD surface of the thermal management aid, the array ofnanotubes affixed to one of either the surface of the die or the CVDDsurface of the thermal management aid.
 2. The apparatus of claim 1wherein the carbon nanotubes of the array of carbon nanotubes areprimarily affixed to the CVDD layer of the thermal management aid. 3.The apparatus of claim 1 wherein the carbon nanotubes of the array ofcarbon nanotubes are primarily affixed to the surface of the circuitdie.
 4. The apparatus of claim 1 wherein the carbon nanotubes of thearray of carbon nanotubes are affixed to both the surface of the circuitdie and the CVDD surface of the thermal management aid.
 5. The apparatusof claim 1 wherein the thermal management aid is an integrated heatspreader
 6. The apparatus of claim 1 wherein the thermal management aidis a heat sink.
 7. The apparatus of claim 1 wherein the array ofsubstantially aligned carbon nanotubes also comprises thermal interfacematerial.
 8. The apparatus of claim 7 wherein the thermal interfacematerial comprises a thermally conductive grease.
 9. Apparatus forcooling a circuit die, comprising: a thermal management aid having aCVDD surface; and an array of substantially aligned carbon nanotubescoupling a surface of the circuit die to the CVDD surface of the thermalmanagement aid, the array of nanotubes affixed to the surface of thedie.
 10. The apparatus of claim 9 wherein the array is also affixed tothe CVDD surface.
 11. The apparatus of claim 9 wherein the array alsocomprises thermally conductive grease.
 12. Apparatus for cooling acircuit die, comprising: a thermal management aid having a CVDD surface;and an array of substantially aligned carbon nanotubes coupling asurface of the circuit die to the CVDD surface of the thermal managementaid, the array of nanotubes affixed to the CVDD surface of the thermalmanagement aid.
 13. The apparatus of claim 12 wherein the apparatus alsocomprises a thermally conductive grease.
 14. The apparatus of claim 12wherein the array is also affixed to the die.
 15. An integrated circuitpackage, comprising: a substrate; a circuit die mounted on the substratea heat sink; a heat spreader thermally coupled to the heat sink andhaving a having a CVDD surface; and an array of substantially alignedcarbon nanotubes coupling a surface of the circuit die to the CVDDsurface of the heat spreader, the array of nanotubes affixed to one ofeither the surface of the circuit die or the CVDD surface of the thermalspreader.
 16. The integrated circuit package of claim 15 wherein thearray affixed to both the surface of the circuit die and the CVDDsurface of the heat spreader.
 17. The integrated circuit package ofclaim 15 wherein the array also comprises thermal grease.
 18. A processfor enhancing heat transfer from a circuit die to a thermal managementaid, comprising: forming a CVDD layer on a thermal management aid;growing an array of nanotubes on one of a surface of the circuit die orthe CVDD layer; and mounting the thermal management aid to the circuitdie with the layer of aligned nanotubes thermally coupling the surfaceof the circuit die to the CVDD layer of the thermal management aid. 19.The process according to claim 18, wherein the growing of a layer ofnanotubes comprises forming the nanotubes on a surface of the die by aplasma-discharge process.
 20. The process according to claim 18, whereinthe growing of a layer of nanotubes comprises forming the nanotubes onthe CVDD layer by a plasma-discharge process.
 21. A process forthermally coupling a circuit die to a thermal management aid comprising:forming a CVDD layer on a thermal management aid; growing a layer ofnanotubes on the CVDD layer; and mounting the thermal management aid tothe die with the layer of nanotubes thermally coupling the surface ofthe die to the CVDD layer of the thermal management aid.
 22. The processaccording to claim 21, wherein the growing operation also comprisesadding thermal interface material to the layer of nanotubes.
 23. Theprocess according to claim 21, also comprising growing a layer ofnanotubes on the surface of the die and the mounting of the thermalmanagement layer to the die also comprises intermeshing the layers ofnanotubes.